In recent years, as semiconductor devices have become higher in integration, functionality, and speed, demand for miniaturization of the semiconductor devices has been growing. To satisfy the demand, various device structures have been proposed for reducing the area occupied by transistors over a substrate. Among them, a field effect transistor having a fin-type structure has drawn attention. The field effect transistor having the fin-type structure is generally called a fin-FET (Fin-Field Effect Transistor), and has an active region made of a semiconductor region (hereinafter referred to as a fin-semiconductor region) having a thin-wall (fin) shape perpendicular to the principal surface of a substrate. In the fin-FET, the both side surfaces of the fin-semiconductor region can be used as channel surfaces, and accordingly the area occupied by transistors over the substrate can be reduced (see, e.g., Patent Document 1 and Non-Patent Document 1).
FIGS. 12(a)-12(d) are views each showing a structure of a conventional fin-FET, of which FIG. 12(a) is a plan view, FIG. 12(b) is a cross-sectional view along the line A-A in FIG. 12(a), FIG. 12(c) is a cross-sectional view along the line B-B in FIG. 12(a), and FIG. 12(d) is a cross-sectional view along the line C-C in FIG. 12(a).
As shown in FIGS. 12(a)-12(d), the conventional fin-FET has a support substrate 101 made of silicon, an insulating layer 102 made of silicon dioxide formed on the support substrate 101, fin-semiconductor regions 103a-103d formed on the insulating layer 102, a gate electrode 105 formed over the fin-semiconductor regions 103a-103d with gate insulating films 104a-104d being interposed therebetween, insulating sidewall spacers 106 formed on the side surfaces of the gate electrode 105, extension regions 107 formed in the both side regions of the fin-semiconductor regions 103a-103d with the gate electrode 105 being interposed therebetween, and source/drain regions 117 formed in the both side regions of the fin-semiconductor regions 103a-103d with the gate electrode 105 and the insulating sidewall spacers 106 being interposed therebetween. The fin-semiconductor regions 103a-103b are disposed on the insulating layer 102 to be arranged at given intervals in a gate width direction. The gate electrode 105 is formed so as to extend over the fin-semiconductor regions 103a-103d in the gate width direction. Each of the extension regions 107 includes a first impurity region 107a formed in the upper portion of each of the fin-semiconductor regions 103a-103d, and second impurity regions 107b formed in the side portions of each of the fin-semiconductor regions 103a-103d. Each of the source/drain regions 117 includes a third impurity region 117a formed in the upper portion of each of the fin-semiconductor regions 103a-103d, and fourth impurity regions 117b formed in the side portions of each of the fin-semiconductor regions 103a-103d. Note that a description and depiction of pocket regions is omitted.
FIGS. 13(a)-13(d) are cross-sectional views showing a method for fabricating the conventional semiconductor device in the order of process steps. Note that FIGS. 13(a)-13(d) correspond to a cross-sectional structure along the line C-C in FIG. 12(a). In FIGS. 13(a)-13(d), the same components as those of the structure shown in FIGS. 12(a)-12(d) are provided with the same reference characters, and an overlapping description is omitted.
First, as shown in FIG. 13(a), a SOI (Silicon On Insulator) substrate is prepared in which a semiconductor layer made of silicon is provided over the support substrate 101 made of silicon with the insulating layer 102 made of silicon dioxide being interposed therebetween. Then, the semiconductor layer is patterned to form the fin-semiconductor region 103b serving as an active region.
Next, as shown in FIG. 13(b), a gate insulating film 104 is formed on the surface of the fin-semiconductor region 103b, and then a polysilicon film 105A is formed over the entire surface of the support substrate 101.
Next, as shown in FIG. 13(c), the polysilicon film 105A and the gate insulating film 104 are successively etched to form the gate electrode 105 over the fin-semiconductor region 103b with the gate insulating film 104b being interposed therebetween. Then, using the gate electrode 105 as a mask, impurity ions are implanted into the semiconductor region 103b to form the extension regions 107 and the pocket regions (not shown).
Next, as shown in FIG. 13(d), an insulating film is formed over the entire surface of the support substrate 101, and then etched back using anisotropic dry etching, thereby forming the insulating sidewall spacers 106 on the side surfaces of the gate electrode 105. Then, using the gate electrode 105 and the insulating sidewall spacers 106 as a mask, impurity ions are implanted into the semiconductor region 103b to form the source/drain regions 117.
By the foregoing process steps, a fin-MISFET (Metal Insulator Semiconductor Field Effect Transistor) having the gate electrode 105 formed over the fin-semiconductor region 103b with the gate insulating film 104b being interposed therebetween can be obtained.
FIG. 14(a) is a cross-sectional view showing the step of forming the extension regions of a fin-FET in Patent Document 1. FIG. 14(b) is a cross-sectional view showing the step of forming the extension regions of a fin-FET in Non-Patent Document 1. Note that FIGS. 14(a) and 14(b) correspond to a cross-sectional structure (prior to the formation of the insulating sidewall spacers 106) along the line B-B in FIG. 12(a). In FIGS. 14(a) and 14(b), the same components as those of the structure shown in FIGS. 12(a)-12(d) are provided with the same reference characters, and an overlying description is omitted.
As shown in FIG. 14(a), in the method disclosed in Patent Document 1, in order to introduce an impurity not only into the upper surfaces of the fin-semiconductor regions 103a-103d, but also into the side surfaces thereof, ions 108a and 108b are implanted at respective implantation angles inclined to the opposite sides of a vertical direction into the fin-semiconductor regions 103a-103d, thereby forming the extension regions 107. In this case, in the upper portions of the fin-semiconductor regions 103a-103d, the first impurity regions 107a are formed in which both of the ions 108a and 108b have been implanted. However, in the side portions of the fin-semiconductor regions 103a-103d, the second impurity regions 107b are formed in which either the ions 108a or the ions 108b have been implanted. That is, when the dosage of the ions 108a and the dosage of the ions 108b are the same, the implantation dosage in each of the first impurity regions 107a has a magnitude double that of the implantation dosage in each of the second impurity regions 107b. 
On the other hand, as shown in FIG. 14(b), in the method disclosed in Non-Patent Document 1, the extension regions 107 are formed in the fin-semiconductor regions 103a-103d using a plasma doping process. When impurity introduction is performed using the plasma doping process, the first impurity regions 107a each having an introduction dosage determined by the balance among introduced ions 109a, adsorbed species (neutral species such as gas molecules and radicals) 109b, and impurities 109c desorbed by sputtering from the fin-semiconductor regions 103a-103d are formed in the upper portions of the fin-semiconductor regions 103a-103d. However, as for the introduction dosage in each of the side portions of the fin-semiconductor regions 103a-103d, it is less affected by the introduced ions 109a or the impurities 109c desorbed by sputtering so that the second impurity regions 107b each having the introduction dosage primarily determined by the adsorbed species 109b are formed in the side portions of the fin-semiconductor regions 103a-103d. As a result, the introduction dosage in the first impurity region 107a is higher than the introduction dosage in the second impurity region 107b by, e.g., about 25%.
Thus, according to the method for forming the extension regions of the conventional fin-FET, the introduction dosage in each of the first impurity regions 107a formed in the upper portions of the fin-semiconductor regions 103a-103d is higher than the introduction dosage in each of the second impurity regions 107b formed in the side portions of the fin-semiconductor regions 103a-103d. In addition, the junction depth of the second impurity region 107b is shallower than the junction depth of the first impurity region 107a. As a result, the sheet resistance, specific resistance, or spreading resistance of the first impurity region 107a is lower than the sheet resistance, specific resistance, or spreading resistance of the second impurity region 107b. Note that, when it is assumed that the sheet resistance of a target object is Rs, the resistivity (specific resistance) thereof is ρ, the thickness (junction depth) thereof is t, and the spreading resistance thereof is ρw, Rs=ρ/t is satisfied. In addition, as represented by a relational expression ρw=CF×k×ρ/(2πr) widely known in the measurement of a spreading resistance, the resistivity (specific resistance) ρ and the spreading resistance ρw are basically in one-to-one relation so that an expression Rs∝ρw/t is obtained.
In the relational expression shown above, CF is a correction term (CF=1 in the case where there is no correction) in which the volume effect of the spreading resistance ρw is considered, k is a correction term (k=1 when the sample is, e.g., p-type silicon, and k=1 to 3 when the sample is, e.g., n-type silicon) in which polarity dependence in a Schottky barrier between a probe and a sample is considered, and r is the radius of curvature of the tip of the probe.
When the fin-FET having such an extension structure is operated, a current flowing in each of the extension regions 107 is localized to the first impurity region 107a having the introduction dosage higher (i.e., sheet resistance lower) than that in the second impurity region 107b. As a result, the problem arises that desired transistor characteristics cannot be obtained.
In the conventional fin-FET, the source/drain regions are also formed using the same ion implantation process or the same plasma doping process as that used to form the extension regions. Accordingly, in the source/drain regions 117 also, the introduction dosage in each of the third impurity regions 117a formed in the upper portions of the fin-semiconductor regions 103a-103d is higher than the introduction dosage in each of the fourth impurity regions 117b formed in the side portions of the fin-semiconductor regions 103a-103d. In addition, the junction depth of the fourth impurity region 117b is shallower than the junction depth of the third impurity region 117a. When the fin-FET having such a source/drain structure is operated, a current flowing in each of the source/drain regions 117 is localized to the third impurity region 117a having the introduction dosage higher (i.e., sheet resistance lower) than that in the fourth impurity region 117b. As a result, the problem arises that desired transistor characteristics cannot be obtained.